The present disclosure relates generally to semiconductor fabrication, and more particularly, to semiconductor fabrication process control.
As performance requirements and throughput demands increase, semiconductor fabrication process control has become even more crucial. However, as process geometries decrease, such as from 13 μm to 90 nanometer, semiconductor manufacturers have struggled to keep process variations at an acceptable level. As such, the processes may suffer from losses in tool productivity, increased operator interaction, yield loss, and higher rework rates, all possibly leading to higher costs. Automated Process Control (APC), which may consist of models and feedback systems among other process control techniques, may help to alleviate some of the variations. However sufficient APC methods are lacking, especially for controlling parameters that are affected by multiple process steps.
The sheet resistance (Rs) of the copper interconnects is one of the parameters that semiconductor manufacturers have had difficulty in maintaining an acceptable variation. For processes such as those with 90 nanometer feature sizes, a copper Rs variation of less than 20% may be required. In addition to these demanding performance requirements, low-k performance goals for the process have, in some instances, required the omission of several etch stop layers compounding the difficulties controlling the copper interconnect processes. One solution to control sheet resistance using APC concerns control of only a single process step, specifically that of deposition of the copper seed layer and teaches controlling the profile of that layer. Another solution to control Rs using APC only concerns control of a CMP process to minimize Rs variation.
Accordingly, it would be desirable to provide process control absent the disadvantages discussed above.